4*4矩阵键盘的FPGA驱动

一、硬件原理

在这里插入图片描述

4*4矩阵键盘有4行与4列，在按键按下时一行与一列即导通。其驱动方法非常简单。本设计中以一定的时间频率分别将每一行的引脚电平拉高，并在拉高某个引脚的同时检测每一列的电平变化，当检测到某列引脚有上升沿跳变时，即为该行与该列导通对应的那个按键被按下。

例如上图中，拉高PD4,此时检测到PD2引脚有上升沿电平跳变，则按键S5被按下。其余同理。

二、Verilog代码实现

//// Company: NanJing University of Information Science & Technology// Engineer: Yang Cheng Yu// // Create Date: 2020/01/13 20:01:50// Design Name: keyboard_4_4// Module Name: keyboard_4_4// Project Name: Clock// Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision:// Revision 0.01 - File Created// Additional Comments:// //module keyboard_4_4(	input 					clk,//时钟	input 					rst,//复位	output reg[3:0] 		c_pin,//行引脚	input[3:0] 				r_pin,//列引脚	output reg[3:0]			key_out//按键编号输出);	reg[15:0] 				div_cnt;//分频计数器	reg[2:0]				state;	reg						cnt_full;//分频计数器计满逻辑	localparam				CHECK_R1=3'b000;//检测R1	localparam				CHECK_R2=3'b001;//检测R2	localparam				CHECK_R3=3'b011;//检测R3	localparam				CHECK_R4=3'b010;//检测R4	//分频计数器逻辑	always@(posedge clk or negedge rst)begin//此处设计每次拉高一行时间为1ms		if(!rst)begin			div_cnt <= 16'd0;			cnt_full <= 1'b0;		end		else			if(div_cnt==16'd49999)begin				div_cnt <= 16'd0;				cnt_full <= 1'b1;			end			else begin				div_cnt <= div_cnt + 1'b1;				cnt_full <= 1'b0;			end	end	//状态组合判断	always@(posedge cnt_full or negedge rst)begin		if(!rst)			state <= CHECK_R1;		else			case(state)				CHECK_R1:					if(cnt_full)						state <= CHECK_R2;					else						state <= CHECK_R1;				CHECK_R2:					if(cnt_full)						state <= CHECK_R3;					else						state <= CHECK_R2;				CHECK_R3:					if(cnt_full)						state <= CHECK_R4;					else						state <= CHECK_R3;				CHECK_R4:					if(cnt_full)						state <= CHECK_R1;					else						state <= CHECK_R4;				default:					state <= state;			endcase	end	//状态机输出逻辑	always@(posedge clk or negedge rst)begin		if(!rst)			c_pin <= 4'b0000;		else			case(state)				CHECK_R1:begin					c_pin <= 4'b1000;					case(r_pin)						4'b1000:key_out <= 4'd0;						4'b0100:key_out <= 4'd1;						4'b0010:key_out <= 4'd2;						4'b0001:key_out <= 4'd3;					endcase				end				CHECK_R2:begin					c_pin <= 4'b0100;					case(r_pin)						4'b1000:key_out <= 4'd4;						4'b0100:key_out <= 4'd5;						4'b0010:key_out <= 4'd6;						4'b0001:key_out <= 4'd7;					endcase				end				CHECK_R3:begin					c_pin <= 4'b0010;					case(r_pin)						4'b1000:key_out <= 4'd8;						4'b0100:key_out <= 4'd9;						4'b0010:key_out <= 4'd10;						4'b0001:key_out <= 4'd11;					endcase				end				CHECK_R4:begin					c_pin <= 4'b0001;					case(r_pin)						4'b1000:key_out <= 4'd12;						4'b0100:key_out <= 4'd13;						4'b0010:key_out <= 4'd14;						4'b0001:key_out <= 4'd15;					endcase				end					default:begin					c_pin <= 4'b0000;					key_out <= 4'd0;				end			endcase	endendmodule

状态转移图

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